System Architectural Design of a Hardware Engine for Moving Target IPv6 Defense Over IEEE 802.3 Ethernet
Author USMA Department
Electrical Engineering and Computer Science
IPv6, Moving target defense, Network processor, FPGA, Hardware, Protocols, Logic gates, Engines, Clocks, Encapsulation, IP networks
The Department of Homeland Security Cyber Security Division (CSD) chose Moving Target Defense as one of the fourteen primary Technical Topic Areas pertinent to securing federal networks and the larger Internet. Moving Target Defense over IPv6 (MT6D) employs an obscuration technique offering keyed access to hosts at a network level without altering existing network infrastructure. This is accomplished through cryptographic dynamic addressing, whereby a new network address is bound to an interface every few seconds in a coordinated manner. The goal of this research is to produce a Register Transfer Level (RTL) network security processor implementation to enable the production of an Application Specific Integrated Circuit (ASIC) variant of MT6D processor for wide deployment. RTL development is challenging in that it must provide system level functions that are normally provided by the Operating System's kernel and supported libraries. This paper presents the architectural design of a hardware engine for MT6D (HE-MT6D) and is complete in simulation. Unique contributions are an inline stream-based network packet processor with a Complex Instruction Set Computer (CISC) architecture, Network Time Protocol listener, and theoretical increased performance over previous software implementations.
J. Sagisi, J. Tront and R. Marchany, "System architectural design of a hardware engine for moving target IPv6 defense over IEEE 802.3 Ethernet," MILCOM 2017 - 2017 IEEE Military Communications Conference (MILCOM), Baltimore, MD, 2017, pp. 551-556. doi: 10.1109/MILCOM.2017.8170846
Military Communications Conference (MILCOM), MILCOM 2017 - 2017 IEEE